The present invention is generally directed to the design of shift register latch scan strings used in the level sensitive scan design approach to logic circuit design. More particularly, the present invention is directed to a logic circuit and test method which is able to provide tests of shift register latch scan strings. In a sense, the present invention permits "testing of the tester".
In order to fully appreciate the operation and advantages of the present invention, it is necessary to consider the level sensitive scan design (LSSD) methodology of logic circuit design. In this design methodology, blocks of combinatorial logic circuitry include input signal lines which are supplied from shift register latches and in turn supply output signal lines to shift register latches. These shift register latches are arranged in scan strings and function in two roles. In normal operation, the shift register latches receive input signals and act as temporary storage for output signals from a first combinatorial logic block to a second, third or subsequent combinatorial logic circuit block. In a test mode of operation, the shift register latches are electrically configured into a single shift register latch scan string which is capable of receiving a string of input signals. By shifting predetermined signal values into the scan string, one may control the signals which are supplied to the combinatorial logic blocks. Likewise, on the output side of the combinatorial logic blocks, output signals may be stored and shifted out for analysis, especially analysis relating to error conditions. In this fashion, each logic block may be tested independently of the function of other blocks.
Since circuits have become much more complex, this aspect of testing has become more important, if not critical in the design and production of very large scale integrated circuit devices. In particular, because of the great complexity of these devices which often contain hundreds of thousands of individual circuit elements, errors in design, implementation or manufacture may occur. Accordingly, it therefore becomes very important to test these logic circuits prior to their being shipped, either by themselves or in a more complicated end product.
The level sensitive scan design methodology has been very successful since it has reduced the test pattern generation task tremendously. This design methodology has allowed testers to scan in a pattern to the shift register latch scan string and scan out resultant data from the scan string. Examples of LSSD rules are found for example in U.S. Pat. No. 4,476,431, issued Oct. 19, 1984 to Arnold Blum; in U.S. Pat. No. 4,513,418, issued Apr. 23, 1985 to Paul H. Bardell and William H. McAnney; and in U.S. Patent No. 4,293,919, issued Oct. 6, 1981 to Sumit DasGupta, et al.; in U.S. Pat. No. 4,687,988, issued Aug. 18, 1987 to Edward B. Eichelberger et al.; and in U.S. Pat. No. 4,503,539, issued Mar. 5, 1985 to William H. McAnney.
The LSSD methodology, as indicated above, has proven to be a fruitful solution to many of the problems of design, fault isolation and test in very large scale integrated circuits. However, if a faulty shift register latch occurs in the scan string, there is no easy way to diagnose and locate the faulty latch. However, because these latches and shift strings play such an important role in the testing of VLSI devices and systems, it is desirable that some mechanism be provided for assuring their proper operation. In particular, the present invention fulfills this role.
In order to more fully grasp the advantages of the present invention, three different time frames are considered. The first time frame occurs after the chip or system has been manufactured or assembled. The second time frame occurs when the chip or system is being employed in normal operation and a test modality is entered, caused for example by the occurrence of an error condition someplace in the machine or circuit. The third time frame occurs when specific tests are being performed on a failed chip or system as a result of the desire to perform physical failure analysis so as to isolate the failed micronet on the malfunctioning chip. In this way, information can be gleaned about the manufacturing or design process. For example, it is easily seen that it is desirable to be able to determine whether the failure is caused by a microscopic piece of dust or by a design error. Product improvement depends on such error analysis. Accordingly, the present invention provides a mechanism to localize the fault to a small group of shift register latches and sometimes to a single faulty SRL by using design considerations described herein.